This invention relates to a semiconductor device, and in particular to a high to ultra-high voltage device such as a diode, a DMOSFET, a DMOS IGBT, a MOSFET or a trench IGBT.
In order to prevent voltage breakdown at the edges of a high voltage semiconductor device, the device (which is typically built in a relatively large silicon wafer) is provided with a termination structure. A standard termination structure utilises a floating ring termination technique having, say, p-type regions (rings) in a surface layer surrounding the active region (of n-type material) of the device.
A typical prior art floating ring termination structure is shown in FIG. 1. The termination structure includes a plurality of p+ floating rings 1 formed in a nxe2x88x92 base layer 2. The rings 1 are formed just below a passivation layer 3 in the form of a surface field oxide layer, and in general alignment with a pxe2x88x92 base 4 and a cathode 5 of the active area (not shown) of the semiconductor device associated with the termination structure. At the extreme edge, the termination structure has a field plate 6 and a channel stopper 7.
The purpose of the p+ floating rings 1 is gradually to release the depletion region, and thus the potential lines from the active area towards the edge of the device. If the separation and the depth of the p+ rings 1 are carefully controlled, the potential lines drop relatively uniformly at the surface between the p+ rings, or between the last p+ ring and the field plate 6, and the breakdown voltage can be close to its ideal value. The termination is said to be successful if it can achieve a breakdown voltage of more than 90% of the bulk value.
The presence of parasitic charge in the passivation layer 3 in the termination area has a strong influence on the depletion layer at the surface, since this charge influences the charge in the depletion layer. It is, therefore, apparent that the higher the doping of the nxe2x88x92 base 2, the less severe the effect of the charge is, since the parasitic charge in the passivation layer 3 may not be sufficient to affect the charge equilibrium at the surface of the device. Hence, the effect of the charge is more pronounced in devices rated at higher voltages. A negative charge in the oxide or passivation layer causes a positive charge layer made of holes to form at the surface in the termination area, which positive charge pushes the potential lines away from the main surface, thus forcing the entire potential to drop at the very edge of the device next to the field plate 6. In other words, each ring 1 does not support effectively part of the breakdown voltage. A positive charge in the oxide or the passivation layer results in an accumulation of electrons at the main surface in the termination area. This tends to retard the spreading and the growth of the depletion layer in between the p+ rings 1, which further results in sharp electric field peaks at the p+ floating ring/nxe2x88x92 surface junctions. This, in turn, leads to premature breakdown. Therefore, charge of either polarity in the oxide or passivation layer can lower the rated breakdown voltage.
The success of a controllable semiconductor device at high or ultra-high voltages is almost entirely determined by a successful implementation of the edge termination. There are three main reasons which make the termination problem more difficult as the voltage ratings increase. Firstly, the number of floating rings increases significantly, and thus the wasted area and the ratio between the wasted area and the active area increases. This results in a poorer yield and a higher on-state voltage. Secondly, as the voltage increases, and accordingly the doping concentration of the base decreases, the device is more prone to parasitic field charge or passivation charge effects, which may cause premature breakdown. Thirdly, as the number of rings increases, the control of the depth and spacing between the rings becomes even tighter than that for a relatively-lower voltage termination, and therefore the termination effectiveness is very susceptible to process variations.
The aim of the invention is to provide a semiconductor device having an edge termination structure which has a substantially reduced parasitic charge in the passivation layer.
The present invention provides a semiconductor device comprising an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device, the edge portion comprising a substrate region of a first semiconductor type, wherein the voltage termination structure comprises at least one first termination region of a second semiconductor type, the or each first termination region having at least one of either second and third termination regions of third and fourth semiconductor types located at substantially opposing edges thereof, the second and third termination regions respectively having a higher semiconductor doping concentration than the edge portion substrate region and a lower semiconductor doping concentration than the first termination region(s).
Advantageously, the edge portion surrounds the active area, the three termination regions of the voltage termination structure extending around the edge portion, and preferably the three termination regions are formed as rings substantially surrounding the active area. The three termination regions may be provided in the region of an upper surface of the edge portion substrate region, the upper edges of the three termination regions being in alignment with one another, and adjacent to the upper surface of the edge portion substrate region.
Preferably, the or each first termination region extends deeper into the edge portion substrate region than the second and third termination regions.
Conveniently, the second and third termination regions of the voltage termination structure are implanted into the edge portion substrate region, and a passivation layer is provided over the upper surface of the edge portion substrate region. Preferably, the passivation layer is an oxide layer.
The semiconductor device of the invention overcomes the problem of parasitic charge in the passivation layer, and so reduces considerably the affect of this charge on the breakdown voltage of the device.
Advantageously, a channel stopper is provided at an extreme edge of the edge portion substrate region, adjacent to the upper edge of the substrate region, and a field plate is provided above the channel stopper.
In a preferred embodiment, the edge portion substrate region is formed of an n-type semiconductor material, and the or each first termination region is formed of a p-type semiconductor material. In this case, the second and third termination regions are formed of n-type material and p-type material, respectively, the p-type material having a lower doping concentration than the p-type material forming the first termination region(s), and the n-type material having a higher doping concentration than the n-type material forming the edge portion substrate region. Preferably, the first semiconductor type material is nxe2x88x92 material, the second semiconductor type material is p+ material, the third semiconductor type material is n material and the fourth semiconductor type material is p material.